The present invention relates to a semiconductor device such as a MOS (Metal Oxide Semiconductor) transistor having a recess structure formed on a SOI (Semiconductor on Insulator) substrate and method for fabricating the same.
A transistor formed by using a SOI substrate is attracting attention as a device having the superior electrical characteristics of a low threshold voltage, a good sub-threshold characteristic, absence of parasitic bipolar effect and so on as compared with the conventional transistor formed by using a bulk semiconductor substrate, and accordingly, researches on the transistor are being energetically conducted.
The SOI substrate has a structure in which an insulating layer is formed on a silicon substrate and a silicon layer (referred to as a SOI layer hereinafter) is formed on the insulating layer. A MOS transistor formed on such a SOI substrate generally has a structure as shown in FIG. 11. in regard to the SOI wafer where an insulating layer 102 and a SOI layer 103 are formed on a silicon substrate 101, a gate electrode 114 is formed on the SOI layer 103 via a gate oxide film 112, and thereafter, low-concentration impurity ions are implanted using the gate electrode 114 as a mask to form LDD (lightly doped drain) regions 115 and 115 on both sides of a channel region 119. Further, oxide film spacers 116 and 116 are formed on the side wall sides of the gate electrode 114, and thereafter, high-concentration ion implantation is executed using the gate electrode 114 and the oxide film spacers 116 and 116 as a mask to form a source junction region 117 and a drain junction region 118. In the thus-formed MOS transistor, the channel region 119 is formed with a small thickness of 50 to 150 nm in order to improve the carrier mobility, and therefore, the source junction region 117 and the drain junction region 118 are similarly reduced in thickness. As a result, the resistances of the source junction region 117 and the drain junction region 118 themselves increase, and this leads to the problem that the operating speed of the MOS transistor is reduced to degrade the device characteristics.
In order to solve the above problems, the following semiconductor device fabricating methods (1) and (2) have conventionally been proposed.
(1) The Semiconductor Device Fabricating Method Disclosed in the Prior Art Reference of Japanese Patent Laid-Open Publication No. HEI 9-8308
FIGS. 12A through 12E are process charts for explaining the semiconductor device fabricating method disclosed in the prior art reference of Japanese Patent Laid-Open Publication No. HEI 9-8308. In the SOI substrate constructed of a silicon substrate 201, an insulating layer 202 and a SOI layer 203, the thickness of the SOI layer 203 is made to have a thickness of 300 to 500 nm. The SOI layer of a portion where a channel region and an LDD region are formed is etched using a photosensitive film 222 as a mask to reduce the film thickness of the portion of the SOI layer 203 to a specified thickness, forming a trench 223 (FIG. 12A). Subsequently, a gate oxide film 212 and a polysilicon layer 213 are deposited on the entire SOI substrate. The polysilicon layer 213 and the gate oxide film 212 are successively etched using a photosensitive film 224 as a mask, and thereafter, the gate oxide film 212 and a gate electrode 214 are formed (FIGS. 12B and 12C). Subsequently, low-concentration impurity ions are implanted into the SOI layer 203 using the gate electrode 214 as a mask, forming an LDD region 215 (FIG. 12D). Subsequently, oxide film spacers 216 and 216 are formed on both side wall sides of the gate electrode 214, and finally high-concentration impurity ions are implanted using the gate electrode 214 and the oxide film spacers 216 as a mask, forming a source junction region 217 and a drain junction region 218 (FIG. 12E).
(2) A Semiconductor Device Fabricating Method Using a LOCOS (Local Oxidation of Silicon) Process
FIGS. 14A through 14D are process charts for explaining a semiconductor device fabricating method using a LOCOS process. First of all, as shown in FIGS. 14A and 14B, in the SOI substrate constructed of a silicon substrate 401, an insulating layer 402 and a SOI layer 403, the channel region is subjected to the LOCOS process, and thereafter, the resulting LOCOS oxide film is totally removed using a nitride film 405 as a mask, forming a recess. Subsequently, as shown in FIG. 14C, a gate oxide film 412 is formed, and thereafter, a polysilicon film 413 is deposited by the CVD (Chemical Vapor Deposition) method on the entire SOI substrate. Subsequently, the polysilicon film 413 is etched back to the surface of the nitride film 405 to form a gate electrode 414. The nitride film is removed, and thereafter, a source junction region and a drain junction region are formed in the SOI layer 403 in a self-alignment manner using the gate electrode 414 as a mask.
In each of the transistors formed on the SOI layers fabricated by the prior art techniques shown in FIGS. 12A through 12E and FIGS. 14A through 14D, the portion where the channel region or the LDD region is formed is set at a specified depth, and the source junction region and the drain junction region can be made thick. Therefore, the transistors have the effect of reducing the resistances of the junction regions.
However, the transistors formed on the SOI layers fabricated by the semiconductor device fabricating method shown in FIGS. 12A through 12E and FIGS. 14A through 14D have the problems as follows.
The semiconductor device fabricating method (1) has the following problem.
According to the semiconductor device fabricating method shown in FIGS. 12A through 12E, the gate electrode 214 is formed by etching with the photosensitive film 224 used as a mask. The position of the photosensitive film 224 that serves as the mask formed through the processes of coating, exposure and developing varies within the range of accuracy of the exposure apparatus. Therefore, the photosensitive film 224 that serves as the mask can not always be formed at the center of the trench region 223.
FIGS. 13A through 13D are process charts when the position of the photosensitive film that serves as the mask is displaced. As shown in FIG. 13A, when a photosensitive film 324 is displaced from the center of the trench toward the source region side (leftward in FIGS. 3A through 3D), then a gate electrode 314 is formed (FIG. 13B). As a result, in the next process for implanting low-concentration impurity ions into the LDD region, there is the structure in which an LDD region 315a located on the source side and an LDD region 315b located on the drain side become asymmetrical (FIG. 13C). Next, when high-concentration impurity ions are implanted into a source junction region 317 and a drain junction region 318, then the transistor comes to have a structure in which the source side and the drain side become asymmetrical about a channel region 319 (FIG. 13D). The degree of asymmetry depends on the accuracy of the exposure apparatus, and the gate electrode cannot always be formed at the center of the trench region. For this reason, it is very difficult to form the gate electrode in the specified position with high reproducibility, and this consequently leads to the problem that the resulting transistors significantly vary in electrical characteristics.
As countermeasures against the above problem, when the trench width is increased so that the LDD regions become equivalent to each other on the source side and the drain side as shown in FIG. 13E, then the size of the transistor increases, resulting in a disadvantage in terms of integration. Furthermore, since a source junction region 325 and a drain junction region 326 located outside the LDD regions 315a and 315b are reduced in thickness, and therefore, the junction regions come to have a great resistance to reduce the operating speed of the transistor.
The semiconductor device fabricating method (2) has the following problem.
According to the semiconductor device fabricating method shown in FIGS. 14A through 14D, a LOCOS oxide film 404 for forming a recess structure is totally removed by wet etching (FIG. 14B), and thereafter, the gate oxide film 412 and the gate electrode 414 are formed. As a result, the gate electrode 414 comes to have a structure in which the gate electrode 414 overlaps the LOCOS end of the SOI layer 403 (FIG. 14D), and this leads to the problem that a leak current attributed to the crystal defect is generated at the LOCOS end of the SOI layer 403.
Furthermore, the side wall shape of the gate electrode 414 becomes a bird""s beak shape that is hard to be controlled, and this makes it difficult to control the implantation of impurities into the source junction region, the drain junction region and the channel region. As a result, the desired transistor structure cannot be obtained, and this causes the problem that the stable characteristics cannot be obtained.
Furthermore, according to the silicide technology for forming a low-resistance silicide on the surfaces of the gate electrode 414 or the source junction region and the drain junction region of the SOI layer 403, the gate electrode 414 has the structure in which the electrode 414 overlaps the LOCOS end of the SOI layer 403. Therefore, it is sometimes the case where a bridge shortcircuit might occur due to the silicide formation between the gate electrode 414 and the source junction region and drain junction region of the SOI layer 403.
Accordingly, the object of the present invention is to provide a semiconductor device capable of reducing the dispersion in electrical characteristics, preventing the occurrence of bridge shortcircuit in the silicide process and operating at high operating speed and method for fabricating the same.
In order to achieve the above object, the present invention provides a semiconductor device having a silicon substrate, an insulating layer formed on the silicon substrate and a SOI layer formed on the insulating layer, comprising:
a channel region formed in the SOI layer;
LDD regions formed on both sides of the channel region of the SOI layer;
a source junction region and a drain junction region formed outside the respective LDD regions of the SOI layer;
a gate electrode which is formed above the channel region via a gate insulating film and both side walls of which have a shape roughly perpendicular to the SOI substrate; and
an oxide film spacer formed on the LDD regions on both side wall sides of the gate electrode, wherein
the source junction region and the drain junction region have a thickness greater than that of the channel region and wherein
the LDD regions have a thickness continuously varying so that the LDD regions become gradually thicker from the channel region side toward the source junction region side and the drain junction region side.
According to the semiconductor device having the above construction, the structure provided with the oxide film spacer that is formed on the LDD regions on both side wall sides of the gate electrode on the channel region comes to have a self-alignment arrangement by using the gate electrode and the oxide film spacer as a mask in the process for implanting impurity ions in the fabricating stage, by which the position of the gate electrode is determined with respect to the positions of the source junction region and the drain junction region outside the LDD region. Therefore, the dispersion in electrical characteristics can be reduced. The source junction region and drain junction region of the SOI layer are made thicker than the channel region, and therefore, the resistances of the source and drain junction regions themselves are reduced. The LDD regions of the SOI layer continuously vary in thickness so that the thickness of the LDD regions gradually increases from the channel region thickness from the channel region side toward the source junction region side and the drain junction region side. Therefore, the increase of capacity between the gate electrode and the LDD region and that between the gate electrode and the source and drain junction regions are restrained. As described above, the operating speed of the transistor can be significantly improved by reducing the resistances of the source and drain junction regions themselves and restraining the increase in capacity between the gate electrode and the source and drain junction regions. Furthermore, the side wall shape of the gate electrode is formed roughly perpendicularly to the SOI substrate, and therefore, the gate electrode does not overlap the source and drain junction regions. In the case where the silicide process is applied, the bridge shortcircuit between the gate electrode and the source and drain junction regions can be prevented.
The present invention also provides a semiconductor device fabricating method comprising the steps of:
successively forming a first oxide film and a nitride film on a SOI substrate constructed of a silicon substrate, an insulating layer and a SOI layer;
forming an opening in the nitride film by removing the nitride film on a portion that becomes a channel region of the SOI layer;
selectively oxidizing the SOI layer and forming a selection oxide film on the remained SOI layer so that a portion that becomes a channel region of the remained SOI layer comes to have a specified thickness, wherein the nitride film in which the opening is formed is used as a mask;
etching the selection oxide film roughly perpendicularly to the SOI substrate until the remained SOI layer is exposed with the nitride film in which the opening is formed used as a mask after the formation of the selection oxide film;
forming a gate oxide film on the remained SOI layer exposed by etching the selection oxide film;
forming a gate electrode made of polysilicon inside the opening of the nitride film by forming a polysilicon layer on the entire SOI substrate on part of which the gate oxide film is formed and etching back the polysilicon layer;
forming a portion that becomes an LDD region in the SOI layer outside a region below the gate electrode by removing the nitride film, the selection oxide film and the first oxide film after the formation of the gate electrode and implanting low-concentration impurity ions into the SOI layer using the gate electrode as a mask;
forming an oxide film spacer on both side wall sides of the gate electrode by forming a second oxide film on the entire SOI substrate where the portion that becomes the LDD region is formed in the SOI layer and subjecting the second oxide film to anisotropic etching; and
forming a source junction region and a drain junction region in the SOI layer outside the region below the gate electrode and the oxide film spacer by implanting high-concentration impurity ions into the SOI layer using the gate electrode and the oxide film spacer as a mask after the formation of the oxide film spacer.
According to the semiconductor device fabricating method of the present invention, the first oxide film and the nitride film are firstly successively formed on the SOI substrate constructed of tho silicon substrate, the insulating layer and the SOI layer, and the opening is formed in the nitride film by removing the nitride film on the portion that becomes the channel region of the SOI layer. Next, the SOI layer is selectively oxidized with the nitride film in which the opening is formed used as a mask so that the portion that becomes the channel region of the SOI layer comes to have the specified thickness, forming on the SOI layer the selection oxide film having the bird""s beak shape of which the sectional shape gradually reduces in thickness toward the outside on both sides. Then, the SOI layer continuously varies in thickness along the bird""s beak shape of the selection oxide film so that the portion (that becomes the channel region) below the opening of the nitride film becomes flat and both sides of the flat portion become gradually thicker toward the outside. Thereafter, by etching the selection oxide film roughly perpendicularly to the SOI substrate with the nitride film in which the opening is formed used as a mask, the portion that becomes the channel region of the SOI layer below the opening of the nitride film is exposed. Then, by forming the gate oxide film on the SOI layer exposed by the etching of the selection oxide film, forming the polysilicon layer on the entire SOI substrate where the gate oxide film is formed and etching back the polysilicon layer, the gate electrode made of polysilicon is formed inside the opening of the nitride film, i.e., on the portion that becomes the channel region of reduced film thickness of the SOI layer. By removing the nitride film, the selection oxide film and the first oxide film after the formation of the gate electrode and implanting low-concentration impurity ions into the SOI layer using the gate electrode as a mask, the portion that becomes the LDD region is formed in the SOI layer outside the region below the gate electrode. Then, by forming the second oxide film on the entire SOI substrate where the portion that becomes the LDD region is formed in the SOI layer and subjecting the second oxide film to anisotropic etching, the oxide film spacer is formed on both side wall sides of the gate electrode. Thereafter, by implanting high-concentration impurity ions into the SOI layer using the gate electrode and the oxide film spacer as a mask, the source junction region and the drain junction region are formed in the SOI layer outside the region below the gate electrode and the oxide film spacer. In this stage, the SOI layer below the oxide film spacer has its impurity concentration maintained low to become the LDD region. By forming the oxide film spacer on the portion where the SOI layer thickness continuously varies, the LDD region continuously varies in thickness so that its thickness gradually increases from the channel region side toward the source junction region side and the drain junction region side. In the semiconductor device fabricated as above, the position of the gate electrode is determined with respect to the positions of the source junction region and the drain junction region outside the LDD region. Therefore, the dispersion in electrical characteristics can be reduced. The source junction region and drain junction region of the SOI layer are made thicker than the channel region. Therefore, the resistances of the source and drain junction regions themselves are reduced. The LDD region of the SOI layer continuously varies in thickness so that its thickness gradually increases from the channel region thickness from the channel region side toward the source junction region side and the drain junction region side. Therefore, the increase of capacity between the gate electrode and the LDD region and of capacity between the gate electrode and the source and drain junction regions are restrained, allowing the operating speed of the transistor to be significantly improved. Furthermore, the side wall shape of the gate electrode is formed roughly perpendicularly to the SOI substrate, and therefore, the gate electrode does not overlap the source and drain junction regions. In the case where the silicide process is applied, the bridge shortcircuit between the gate electrode and the source and drain junction regions can be prevented.
The present invention also provides a semiconductor device having a silicon substrate, an insulating layer formed on the silicon substrate and a SOI layer formed on the insulating layer, comprising:
a channel region formed in the SOI layer;
LDD regions formed on both sides of a channel region of the SOI layer;
a source junction region and a drain junction region formed outside the respective LDD regions of the SOI layer;
a gate electrode which is formed on the channel region via a gate insulating film and both the side walls of which have a shape roughly perpendicular to the SOI substrate; and
an oxide film spacer formed on the LDD regions on both side wall sides of the gate electrode, wherein
the source junction region and the drain junction region have a thickness greater than each of those of the channel region and the LDD region and wherein
the source junction region and the drain junction region continuously vary in thickness so that regions in the vicinity of the LDD region have a thickness that becomes gradually thicker from the LDD region side toward the outside.
According to the semiconductor device having the above construction, the structure provided with the oxide film spacer that is formed on the LDD regions on both side wall sides of the gate electrode on the channel region comes to have a self-alignment arrangement by using the gate electrode and the oxide film spacer as a mask in the process for implanting impurity ions in the fabricating stage, by which the position of the gate electrode is determined with respect to the positions of the source junction region and the drain junction region outside the LDD region. Therefore, the dispersion in electrical characteristics can be reduced. The source junction region and drain junction region of the SOI layer are made thicker than the channel region and the LDD region, by which the resistances of the source and drain junction regions themselves are reduced. The source junction region and the drain junction region continuously vary in thickness so that the regions in the vicinity of the LDD region have a thickness that becomes gradually thicker from the LDD region side toward the outside. Therefore, the increase of capacity between the gate electrode and the LDD region and of capacity between the gate electrode and the source and drain junction regions are restrained. As described above, the operating speed of the transistor can be significantly improved by reducing the resistances of the source and drain junction regions themselves and restraining the increase of capacity between the gate electrode and the source and drain junction regions. Furthermore, the side wall shape of the gate electrode is formed roughly perpendicularly to the SOI substrate, and therefore, the gate electrode does not overlap the source and drain junction regions. In the case where the silicide process is applied, the bridge shortcircuit between the gate electrode and the source and drain junction regions can be prevented.
The present invention also provides a semiconductor device fabricating method comprising the steps of:
successively forming a first oxide film and a first nitride film on a SOI substrate constructed of a silicon substrate, an insulating layer and a SOI layer;
forming an opening in the first nitride film by removing a specified region of the first nitride film;
selectively oxidizing the SOI layer and forming a selection oxide film on the remained SOI layer so that a portion that becomes a channel region of the remained SOI layer comes to have a specified thickness, wherein the nitride film in which the opening is formed is used as a mask;
forming a nitride film spacer on both side wall sides of the opening of the first nitride film by forming a second nitride film on the entire SOI substrate where the selection oxide film is formed and etching back the second nitride film by anisotropic etching until the selection oxide film is exposed;
etching the selection oxide film roughly perpendicularly to the SOI substrate until the remained SOI layer is exposed using the first nitride film and the nitride film spacer as a mask after the formation of the nitride film spacer;
forming a gate oxide film on the remained SOI layer exposed by etching the selection oxide film;
forming a gate electrode made of polysilicon inside the opening of the first nitride film by forming a polysilicon layer on the entire SOI substrate on which the gate oxide film is formed and etching back the polysilicon layer;
forming a portion that becomes an LDD region in the SOI layer outside a region below the gate electrode by removing the first nitride film, the nitride film spacer, the selection oxide film and the first oxide film after the formation of the gate electrode and implanting low-concentration impurity ions into the SOI layer using the gate electrode as a mask;
forming an oxide film spacer on both side wall sides of the gate electrode by forming a second oxide film on the entire SOI substrate where the portion that becomes the LDD region is formed in the SOI layer and subjecting the second oxide film to anisotropic etching; and
forming a source junction region and a drain junction region in the SOI layer outside the region below the gate electrode and the oxide film spacer by implanting high-concentration impurity ions into the SOI layer using the gate electrode and the oxide film spacer as a mask after the formation of the oxide film spacer.
According to the semiconductor device fabricating method of the present invention, the first oxide film and the first nitride film are firstly successively formed on the SOI substrate constructed of the silicon substrate, the insulating layer and the SOI layer, and the opening is formed in the first nitride film by removing the specified region of the first nitride film. Next, the SOI layer is selectively oxidized with the first nitride film in which the opening is formed used as a mask so that the portion that becomes the channel region of the SOI layer comes to have the specified thickness, forming on the SOI layer the selection oxide film having the bird""s beak shape of which the sectional shape gradually reduces in thickness toward the outside on both sides. Then, the SOI layer continuously varies in thickness along the bird""s beak shape of the selection oxide film so that the portion below the opening of the nitride film becomes flat and both sides of the flat portion become gradually thicker toward the outside. Thereafter, by forming the second nitride film on the entire SOI substrate where the selection oxide film is formed and etching back the second nitride film. by anisotropic etching until the selection oxide film is exposed, the nitride film spacer is formed on both side wall sides of the opening of the first nitride film. Thereafter, by etching the selection oxide film roughly perpendicularly to the SOI substrate until the SOI layer is exposed using the first nitride film and the nitride film spacer as a mask, the portion of the SOI layer below the opening of the first nitride film is exposed except for the region below the nitride film spacer. Then, by forming the gate oxide film on the SOI layer exposed by the etching of the selection oxide film, forming the polysilicon layer on the entire SOI substrate where the gate oxide film is formed and etching back the polysilicon layer, the gate electrode made of polysilicon is formed inside the opening of the first nitride film. By removing the first nitride film, the nitride film spacer, the selection oxide film and the first oxide film after the formation of the gate electrode and implanting low-concentration impurity ions into the SOI layer using the gate electrode as a mask, the portion that becomes the LDD region is formed in the SOI layer outside the region below the gate electrode. Then, by forming the second oxide film on the entire SOI substrate where the portion that becomes the LDD region is formed in the SOI layer and subjecting the second oxide film to anisotropic etching, the oxide film spacer is formed on both side wall sides of the gate electrode. Thereafter, by implanting high-concentration impurity ions into the SOI layer using the gate electrode and the oxide film spacer as a mask, the source junction region and the drain junction region are formed in the SOI layer outside the region below the gate electrode and the oxide film spacer. In this stage, the SOI layer below the oxide film spacer has its impurity concentration maintained low to become the LDD region. By forming the oxide film spacer on the flat portion of reduced film thickness of the SOI layer, the LDD region comes to have the same thickness as that of the channel region, while the source junction region and the drain junction region continuously vary in thickness go that the regions in the vicinity of the LDD region have a thickness that becomes gradually thicker from the LDD region side toward the outside. In the semiconductor device fabricated as above, the position of the gate electrode is determined with respect to the positions of the source junction region and the drain junction region outside the LDD region. Therefore, the dispersion in electrical characteristics can be reduced. The source junction region and drain junction region of the SOI layer are made thicker than the channel region. Therefore, the resistances of the source and drain junction regions themselves are reduced. The LDD region of the SOI layer comes to have the same thickness as that of the channel region having a small film thickness, and therefore, the increase of capacity between the gate electrode and the LDD region and that between the gate electrode and the source and drain junction regions are restrained, allowing the operating speed of the transistor to be significantly improved. Furthermore, the side wall shape of the gate electrode is formed roughly perpendicularly to the SOI substrate, and therefore, the gate electrode does not overlap the source and drain junction regions. In the case where the silicide process is applied, the bridge shortcircuit between the gate electrode and the source and drain junction regions can be prevented.
The present invention also provides a semiconductor device fabricating method comprising the steps of:
successively forming a first oxide film and a first nitride film on a SOI substrate constructed of a silicon substrate, an insulating layer and a SOI layer;
forming an opening in the first nitride film by removing a specified region of the first nitride film;
selectively oxidizing the SOI layer and forming a selection oxide film on the remained SOI layer so that a portion that becomes a channel region of the remained SOI layer comes to have a specified thickness, wherein the nitride film in which the opening is formed is used as a mask;
etching the selection oxide film roughly perpendicularly to the SOI substrate until the remained SOI layer is exposed with the first nitride film in which the opening is formed used as a mask after the formation of the selection oxide film;
forming a second oxide film on the remained SOI layer exposed by etching the selection oxide film;
forming a nitride film spacer on both side wall sides of the opening of the first nitride film by forming a second nitride film on the entire SOI substrate on which the second oxide film is formed and etching back the second nitride film by anisotropic etching until the second oxide film is exposed;
removing the exposed, region of the second oxide film after the formation of the nitride film spacer and forming a gate oxide film on the SOI layer exposed by the removal of the second oxide film;
forming a gate electrode made of polysilicon inside the opening of the first nitride film by forming a polysilicon layer on the entire SOI substrate on part of which the gate oxide film is formed and etching back the polysilicon layer;
forming a portion that becomes an LDD region in the SOI layer outside a region below the gate electrode by removing the first nitride film, the nitride film spacer, the selection oxide film and the first oxide film after the formation of the gate electrode and implanting low-concentration impurity ions into the SOI layer using the gate electrode as a mask;
forming an oxide film spacer on both side wall sides of the gate electrode by forming a second oxide film on the entire SOI substrate where the portion that becomes the LDD region is formed in the SOI layer and subjecting the second oxide film to anisotropic etching; and
forming a source junction region and a drain junction region in the SOI layer outside the region below the gate electrode and the oxide film spacer by implanting high-concentration impurity ions into the SOI layer using the gate electrode and the oxide film spacer as a mask after the formation of the oxide film spacer.
According to the semiconductor device fabricating method of the present invention, the first oxide film and the first nitride film are firstly successively formed on the SOI substrate constructed of the silicon substrate, the insulating layer and the SOI layer, and the opening is formed in the first nitride film by removing the specified region of the first nitride film. Next, the SOI layer is selectively oxidized with the first nitride film in which the opening is formed used as a mask so that the portion that becomes the channel region of the SOI layer comes to have the specified thickness, forming on the SOI layer the selection oxide film having the bird""s beak shape of which the sectional shape gradually reduces in thickness toward the outside on both sides. Then, the SOI layer continuously varies in thickness along the bird""s beak shape of the selection oxide film so that the portion below the opening of the first nitride film becomes flat and both sides of the flat portion become gradually thicker toward the outside. Thereafter, by etching the selection oxide film roughly perpendicularly to the SOI substrate with the first nitride film in which the opening is formed used as a mask, the portion of the SOI layer below the opening of the first nitride film is exposed. Then, by forming the second oxide film on the SOI layer exposed by the etching of the selection oxide film, forming the second nitride film on the entire SOI substrate on which the second oxide film has been formed and etching back the second nitride film by anisotropic etching until the second oxide film is exposed, the nitride film spacer is formed on both side wall sides of the opening of the first nitride film. By removing the exposed region of the second oxide film after the formation of the nitride film spacer, forming the gate oxide film on the SOI layer exposed by the removal of the second oxide film, forming the polysilicon layer on the entire SOI substrate where the gate oxide film is formed and etching back the polysilicon layer, the gate electrode made of polysilicon is formed inside the opening of the first nitride film. By removing the first nitride film, the nitride film spacer, the selection oxide film and the first oxide film after the formation of the gate electrode and implanting low-concentration impurity ions into the SOI layer using the gate electrode as a mask, the portion that becomes the LDD region is formed in the SOI layer outside the region below the gate electrode. Then, by forming the second oxide film on the entire SOI substrate where the portion that becomes the LDD region is formed in the SOI layer and subjecting the second oxide film to anisotropic etching, the oxide film spacer is formed on both side wall sides of the gate electrode. Thereafter, by implanting high-concentration impurity ions into the SOI layer using the gate electrode and the oxide film spacer as a mask, the source junction region and the drain junction region are formed in the SOI layer outside the region below the gate electrode and the oxide film spacer. In this stage, the SOI layer below the oxide film spacer has its impurity concentration maintained low to become the LDD region. By forming the oxide film spacer on the flat portion of reduced film thickness of the SOI layer, the LDD region comes to have the same thickness as that of the channel region, while the source junction region and the drain junction region continuously vary in thickness so that the regions in the vicinity of the LDD region have a thickness that becomes gradually thicker from the LDD region side toward the outside. In the semiconductor device fabricated as above, the position of the gate electrode is determined with respect to the positions of the source junction region and the drain junction region outside the LDD region. Therefore, the dispersion in electrical characteristics can be reduced. The source junction region and drain junction region of the SOI layer are made thicker than the channel region. Therefore, the resistances of the source and drain junction regions themselves are reduced. The LDD region of the SOI layer comes to have the same thickness as that of the channel region having a small film thickness, and therefore, the increase of capacity between the gate electrode and the LDD region and that between the gate electrode and the source and drain junction regions are restrained, allowing the operating speed of the transistor to be significantly improved. Furthermore, the side wall shape of the gate electrode is formed roughly perpendicularly to the SOI substrate, and therefore, the gate electrode. does not overlap the source and drain junction regions. In the case where the silicide process is applied, the bridge shortcircuit between the gate electrode and the source and drain junction regions can be prevented.
The present invention also provides a semiconductor device fabricating method comprising the steps of:
successively forming a first oxide film and a first nitride film on a SOI substrate constructed of a silicon substrate, an insulating layer and a SOI layer;
forming an opening in the first nitride film by removing a specified region of the first nitride film;
selectively oxidizing the SOI layer and forming a selection oxide film on the remained SOI layer so that a portion that becomes a channel region of the remained SOI layer comes to have a specified thickness, wherein the nitride film in which the opening is formed is used as a mask;
forming a first nitride film spacer on both side wall sides of the opening of the first nitride film by forming a second nitride film on the entire SOI substrate where the selection oxide film is formed and etching back the second nitride film by anisotropic etching until the selection oxide film is exposed;
etching the selection oxide film roughly perpendicularly to the SOI substrate until the SOI layer is exposed using the first nitride film and the first nitride film spacer as a mask after the formation of the first nitride film spacer;
forming a second oxide film on the SOI layer exposed by etching the selection oxide film;
forming a second nitride film spacer on both side wall sides of the first nitride film spacer in the opening of the first nitride film by forming a third nitride film on the entire SOI substrate after the formation of the second oxide film and etching back the third nitride film by anisotropic etching until the second oxide film is exposed;
removing the exposed region of the second oxide film after the formation of the second nitride film spacer and forming a gate oxide film on the SOI layer exposed by the removal of the second oxide film;
forming a gate electrode made of polysilicon inside the opening of the first nitride film by forming a polysilicon layer on the entire SOI substrate where the gate oxide film is formed and etching back the polysilicon layer;
forming a portion that becomes an LDD region in the SOI layer outside a region below the gate electrode by removing the first nitride film, the first nitride film spacer, the second nitride film spacer, the selection oxide film and the first oxide film after the formation of the gate oxide film and implanting low-concentration impurity ions into the SOI layer using the gate electrode as a mask;
forming an oxide film spacer on both side wall sides of the gate electrode on a portion that becomes the LDD region of the SOI layer by forming a second oxide film on the entire SOI substrate where the portion that becomes the LDD region is formed in the SOI layer and subjecting the second oxide film to anisotropic etching; and
forming a source junction region and a drain junction region in the SOI layer outside the region below the gate electrode and the oxide film spacer by implanting high-concentration impurity ions into the SOI layer using the gate electrode and the oxide film spacer as a mask after the formation of the oxide film spacer.
According to the semiconductor device fabricating method of the present invention, the first oxide film and the first nitride film are firstly successively formed on the SOI substrate constructed of the silicon substrate, the insulating layer and the SOI layer, and the opening is formed in the first nitride film by removing the specified region of the first nitride film. Next, the SOI layer is selectively oxidized with the first nitride film in which the opening is formed used as a mask so that the portion that becomes the channel region of the SOI layer comes to have the specified thickness, forming on the SOI layer the selection oxide film having the bird""s beak shape of which the sectional shape gradually reduces in thickness toward the outside on both sides. Then, the SOI layer continuously varies in thickness along the bird""s beak shape of the selection oxide film so that the portion below the opening of the first nitride film becomes flat and both sides of the flat portion become gradually thicker toward the outside. Thereafter, by forming the second nitride film on the entire SOI substrate where the selection oxide film is formed and etching back the second nitride film by anisotropic etching until the selection oxide film is exposed, the first nitride film spacer is formed on both side wall sides of the opening of the first nitride film. Then, by etching the selection oxide film roughly perpendicularly to the SOI substrate using the first nitride film and the first nitride film spacer as a mask after the formation of the first nitride film spacer, the portion of the SOI layer below the opening of the first nitride film is exposed except for the region below the first nitride film spacer. Then, by forming a second oxide film on the SOI layer exposed by the etching of the selection oxide film, thereafter forming the third nitride film on the entire SOI substrate and etching back the third nitride film by anisotropic etching until the second oxide film is exposed, the second nitride film spacer is formed on both side wall sides of the first nitride film spacer in the opening of the first nitride film. By removing the exposed region of the second oxide film after the formation of the second nitride film spacer, forming the gate oxide film on the SOI layer exposed by the removal of the second oxide film, forming the polysilicon layer on the entire SOI substrate where the gate oxide film is formed and etching back the polysilicon layer, the gate electrode made of polysilicon is formed inside the opening of the first nitride film. By removing the first nitride film, the first nitride film spacer, the second nitride film spacer, the selection oxide film and the first oxide film after the formation of the gate oxide film and implanting low-concentration impurity ions into the SOI layer using the gate electrode as a mask, the portion that becomes the LDD region is formed in the SOI layer outside the region below the gate electrode. Then, by forming the second oxide film on the entire SOI substrate where the portion that becomes the LDD region is formed in the SOI layer and subjecting the second oxide film to anisotropic etching, the oxide film spacer is formed on the region that becomes the LDD region of the SOI layer on both side wall sides of the gate electrode. Thereafter, by implanting high-concentration impurity ions into the SOI layer using the gate electrode and the oxide film spacer as a mask, the source junction region and the drain junction region are formed in the SOI layer outside the region below the gate electrode and the oxide film spacer. In this stage, the SOI layer below the oxide film spacer has its impurity concentration maintained low to become the LDD region. By forming the oxide film spacer on the flat portion of reduced film thickness of the SOI layer, the LDD region comes to have the same thickness as that of the channel region, while the source junction region and the drain junction region continuously vary in thickness so that the regions in the vicinity of the LDD region have a thickness that becomes gradually thicker from the LDD region side toward the outside. In the semiconductor device fabricated as above, the position of the gate electrode is determined with respect to the positions of the source junction region and the drain junction region outside the LDD region. Therefore, the dispersion in electrical characteristics can be reduced. The source junction region and drain junction region of the SOI layer are made thicker than the channel region. Therefore, the resistances of the source and drain junction regions themselves are reduced. The LDD region of the SOI layer comes to have the same thickness as that of the channel region having a small film thickness, and therefore, the increase of capacity between the gate electrode and the LDD region and that between the gate electrode and the source and drain junction regions are restrained, allowing the operating speed of the transistor to be significantly improved. Furthermore, the side wall shape of the gate electrode is formed roughly perpendicularly to the SOI substrate, and therefore, the gate electrode does not overlap the source and drain junction regions. In the case where the silicide process is applied, the bridge shortcircuit between the gate electrode and the source and drain junction regions can be prevented.
In one embodiment, the channel region of the SOI layer has a thickness of 5 to 100 nm, and the source junction region and the drain junction region of the SOI layer have a thickness of 50 to 500 nm.
According to the semiconductor device of the above embodiment, the channel region of the SOI layer becomes a completely depleted type to have an improved degree of carrier mobility when the thickness is within the range of 5 to 50 nm and becomes a partially depleted type to have practically sufficient carrier mobility when the thickness is within the range of 50 to 100 nm. If the thickness of the channel region is smaller than 5 nm, then the film thickness control is difficult to increase the variation in electrical characteristics to a disadvantage. If the thickness of the channel region exceeds 100 nm, then a reduction in the degree of carrier mobility emerges as a problem. The source junction region and drain junction region of the SOI layer are allowed to have a reduced resistance when the thickness is within the range of 50 to 500 nm. However, if the thickness is smaller than 50 nm, then the resistance becomes high to a disadvantage. If the thickness of each of the source junction region and drain junction region of the SOI layer exceed 500 nm, then much time is required for the formation of the SOI layer, and the reduction in time of the fabricating process cannot easily be achieved.
In one embodiment, the insulating layer of the SOI substrate is either the oxide film or the nitride film.
According to the semiconductor device of the above embodiment, the monocrystal thin film can easily be formed as the SOI layer on the insulating layer that serves as the foundation by using the oxide film or nitride film of the semiconductor material of the SOI layer formed on the insulating layer as the insulating layer of the SOI layer.